1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a universal logic cell, a semiconductor device using the universal logic cell, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
A master slice method which is a semi-custom method is publicly known as one of conventional methods of developing a semiconductor device. As one type of the master slice method, a technique called “structured ASIC (Application Specific Integrated Circuit)” is proposed.
According to the structured ASIC, for example, three lower layers of all six interconnection layers are commonly utilized as “common interconnection layers”, and the remaining three upper layers are provided as “customize interconnection layers”. In the common interconnection layers as the lower layers, such components as interconnections and nodes between transistors, a power supply line, a ground line and the like are formed in advance. A multipurpose macro cell which includes the above-mentioned common interconnection layers and is formed on a chip beforehand is called a “universal logic cell”. The universal logic cell includes not only a layer in which transistors are formed but also the common interconnection layers. In the universal logic cell, the nodes between transistors are particularly formed in a top layer of the above-mentioned common interconnection layers. This makes it possible to connect between these nodes arbitrarily with using interconnections in the customize interconnection layers provided on the common interconnection layers.
More specifically, a plurality of the universal logic cells having such structures are arranged on a chip in a matrix form. Then, in accordance with a desired circuit required by a customer, appropriate interconnections are designed in the customize interconnection layers which is the upper layers. This makes it possible to decrease TAT (Turn Around Time) and to reduce manufacturing costs. An important point in the structured ASIC is “flexibility of the universal logic cell” which is necessary for realizing the circuit required by the customer.
Japanese Laid Open Patent Application 2002-198801 discloses a technique which uses such a universal logic cell. The universal logic cell is a two-input multiplexer having three inverters, two transfer gates and a plurality of nodes. By appropriately connecting between some of the nodes, a NAND circuit, a NOR circuit, an EXOR circuit, or an EXNOR circuit is realized.
In developing the structured ASIC, it is also necessary to realize a “delay circuit” by using such a universal logic cell. The delay circuit is used, for example, to satisfy a setup condition and a hold condition with respect to a sequential circuit such as a flip-flop circuit. In particular, the longer delay time is required as a clock skew in a clock distribution interconnection becomes larger. For this reason, it is desired to realize a delay circuit capable of providing a sufficient delay time with the use of the universal logic cell and the customize interconnection layers. Here, it is preferable in terms of costs that the number of the universal logic cells used for realizing such a delay circuit is as small as possible. In other words, it is desired to realize a delay circuit with which longer delay time can be obtained with fewer universal logic cells, namely, an “efficient” delay circuit.
Japanese Patent Publication No. 2545461 discloses a configuration of a two-input multiplexer (an output selection circuit) of a typical conventional semiconductor device. The circuit is a complementary-type MOS circuit in which outputs of first and second inverters having complementary MOS configurations are wired-OR connected with outputs of first and second tristate circuits consisting of first and second transmission gates. Here, drains of respective of a P-channel MOS transistor and an N-channel MOS transistor of each of the first and second inverters are connected to sources or drains of respective of a P-channel MOS transistor and an N-channel MOS transistor of the corresponding one of the first and second transmission gates in the first and second tristate circuits. The drains of the P-channel MOS transistor and the N-channel MOS transistor of each of the first and second inverters are designed to be disconnected from each other. Also, the first and the second transmission gates are connected in common to a positive phase control signal line and a negative phase control signal line that is delayed from the former.